wiki:GIR3.2_ERM

Version 21 (modified by lnevers@bbn.com, 8 years ago) (diff)

--

Embedded Real-Time Measurements Evaluation

The Embedded Real-Time Measurements(ERM) project deliverable includes two components: the NetFPGA hardware source code, and simulation source code used in developing an experiment to highlight the advantages of the ERM system.

The images validated in the first evaluation effort were the ERM Simulation Source Code and the NetFPGA Hardware Source Code. Both packages were attachments at the GENI ERM page, but are no longer available at the page.

The images validated in the second evaluation effort were the ERM Simulation Source Code and the ERM NetFPGA Hardware Source Code. Both packages were attached to the Embedded Real-Time Measurements page.

First Evaluation Time Frame: October 20th and 24th, 2011 Second Evaluation Time Frame: November 2, 2011

Embedded Real-Time Measurements Findings

The evaluation of the ERM packages focused mainly on documentation and packaging, due to the run time platform not being available for this evaluation.

The First evaluation findings were captured in these emails:

A second evaluation was completed after new packages were made available on November 1, 2011.

Embedded Real-Time Measurements How-to

Second Evaluation Two Packages were made available for the second ERM evaluation:

Simulation Source Code Package

Unpacked the Simulation Source Code Package:

$ unzip ERM-Simulator.v.1.zip 
Archive:  ERM-Simulator.v.1.zip
   creating: GENI 10 Simulations 2/
  inflating: GENI 10 Simulations 2/.DS_Store  
   creating: __MACOSX/
   creating: __MACOSX/GENI 10 Simulations 2/
  inflating: __MACOSX/GENI 10 Simulations 2/._.DS_Store  
   creating: GENI 10 Simulations 2/.svn/
  inflating: GENI 10 Simulations 2/.svn/entries  
   creating: GENI 10 Simulations 2/.svn/prop-base/
   creating: GENI 10 Simulations 2/.svn/props/
   creating: GENI 10 Simulations 2/.svn/text-base/
  inflating: GENI 10 Simulations 2/.svn/text-base/arrive.m.svn-base  
  inflating: GENI 10 Simulations 2/.svn/text-base/configOXC.m.svn-base  
  inflating: GENI 10 Simulations 2/.svn/text-base/constants.m.svn-base  
  inflating: GENI 10 Simulations 2/.svn/text-base/crosstalk.m.svn-base  
  inflating: GENI 10 Simulations 2/.svn/text-base/deconfigOXC.m.svn-base  
  inflating: GENI 10 Simulations 2/.svn/text-base/depart.m.svn-base  
  inflating: GENI 10 Simulations 2/.svn/text-base/dijkstra.m.svn-base  
  inflating: GENI 10 Simulations 2/.svn/text-base/exprnd.m.svn-base  
  inflating: GENI 10 Simulations 2/.svn/text-base/hop_mat.m.svn-base  
  inflating: GENI 10 Simulations 2/.svn/text-base/imp_cons.m.svn-base  
  inflating: GENI 10 Simulations 2/.svn/text-base/InputParam.txt.svn-base  
  inflating: GENI 10 Simulations 2/.svn/text-base/main.m.svn-base  
  inflating: GENI 10 Simulations 2/.svn/text-base/mb2bin.m.svn-base  
  inflating: GENI 10 Simulations 2/.svn/text-base/mini.m.svn-base  
  inflating: GENI 10 Simulations 2/.svn/text-base/nam.m.svn-base  
  inflating: GENI 10 Simulations 2/.svn/text-base/num_bin.m.svn-base  
  inflating: GENI 10 Simulations 2/.svn/text-base/nxt.m.svn-base  
  inflating: GENI 10 Simulations 2/.svn/text-base/parameters.m.svn-base  
  inflating: GENI 10 Simulations 2/.svn/text-base/phy_topology.m.svn-base  
  inflating: GENI 10 Simulations 2/.svn/text-base/RandSD.m.svn-base  
  inflating: GENI 10 Simulations 2/.svn/text-base/sorting.m.svn-base  
  inflating: GENI 10 Simulations 2/.svn/text-base/timing.m.svn-base  
  inflating: GENI 10 Simulations 2/.svn/text-base/wave_assign.m.svn-base  
   creating: GENI 10 Simulations 2/.svn/tmp/
   creating: GENI 10 Simulations 2/.svn/tmp/prop-base/
   creating: GENI 10 Simulations 2/.svn/tmp/props/
   creating: GENI 10 Simulations 2/.svn/tmp/text-base/
  inflating: GENI 10 Simulations 2/arrive.m  
  inflating: GENI 10 Simulations 2/configOXC.m  
  inflating: GENI 10 Simulations 2/constants.m  
  inflating: GENI 10 Simulations 2/crosstalk.m  
  inflating: GENI 10 Simulations 2/deconfigOXC.m  
  inflating: GENI 10 Simulations 2/depart.m  
  inflating: GENI 10 Simulations 2/dijkstra.m  
  inflating: GENI 10 Simulations 2/exprnd.m  
  inflating: GENI 10 Simulations 2/hop_mat.m  
  inflating: GENI 10 Simulations 2/imp_cons.m  
  inflating: GENI 10 Simulations 2/InputParam.txt  
  inflating: GENI 10 Simulations 2/main.m  
  inflating: __MACOSX/GENI 10 Simulations 2/._main.m  
  inflating: GENI 10 Simulations 2/mb2bin.m  
  inflating: GENI 10 Simulations 2/num_bin.m  
  inflating: GENI 10 Simulations 2/nxt.m  
  inflating: GENI 10 Simulations 2/parameters.m  
  inflating: GENI 10 Simulations 2/phy_topology.m  
  inflating: GENI 10 Simulations 2/RandSD.m  
  inflating: GENI 10 Simulations 2/README.txt  
  inflating: GENI 10 Simulations 2/sorting.m  
  inflating: GENI 10 Simulations 2/timing.m  
  inflating: GENI 10 Simulations 2/wave_assign.m 
  $ cd GENI\ 10\ Simulations\ 2/

The package includes a README.txt, which provides an overview of the Simulation Package, functionality new to the release, information about simulator files and viewing results:

GENI and Columbia University proprietary
Authors: Lightwave Research Laboratory
Last Modified: March 2011
All rights reserved
Discrete Event Simulations of Optical Mesh Network (ERM Simulator)
**********************************************************************************
Release: Version 1
Date:  March 2011.
Contact Email: bbathula@ee.columbia.edu; bgsquare@gmail.com
----------------------------------------------------------------------------------
Disclaimer: This software does not come with guarantees !
----------------------------------------------------------------------------------

---------------------------------------
Scope of the Simulation Package:
---------------------------------------
This simulation tool emulates the architecture of the ERM-box, deployed on the large scale networks. Peformance of large scale networks enabled with ERM-box capabilities can be simulated. Impairments in the optical-layer, such as ASE noise and crosstalk in the wavelength switches can be computed. 

----------------------------------------
Functionalities present in this release:
----------------------------------------
* Discrete event simulations of optical mesh networks.
* Events are the arrival and departure of the lightpath demands according to the Poission distribution and exponential service times.
* This simulator can perform, unicast, anycast communication paradigms. In the case of multicast, the light-trees are configured in the network, where the optical switches (ROADMS) perform the light splitting.
* The routing used in the simulator is Shortest-path (OSPF) and the wavelength assignments can be random or first-fit.
* Impairment-aware RWA algorithms are implemented via a Quality-of-Transmission (QoT) estimator.
* Rudimentary energy models are implemented for the optical physical layer.
* Control signaling latencies are modeled.
* Simulator can be scalable to wavelengths and the network topologies.
* Large scale mesh networks are considered.

----------------------
Running the simulator:
----------------------
* The main file is "main.m". 
* The input parameters file used to run the "main.m"  is "InputParam.txt"
* The file "InputParam.txt" consists of the description of the parameters and their values.
* Input Data in "InputParam.txt" should be of the order: 
  1) Number of Requests: More the number of requests (1e6), the statical averages approach steady state values.
  2) Topology Number: The topology numbers can be found in file "phy_topology.m". Ring, Torus mesh, NSFNET, 24 node US mesh Network, CONUS CORONET are implemented.
  3) Number of Wavelengths: This is the number of wavelengths that are used in the network. Each link in the network can multiplex this number of wavelengths.
  4) Q-factor threshold: Quality factor of the signal that is required. 
  5) Routing Method (Distance -1, Hop -2): Distance routing is OSPF and hop routing is consdering the weight if the each link in the network as unity.
  6) Lower limit (Network Load): Starting network load (Erlangs)
  7) Increment Network Load: Incremental network load (Erlangs)
  8) Upper limit Network Load: Maximum network load (Erlangs)
  9) Probable number of destinations (set D_s): D_s=1 for unicast; D_s= k > 1 for anycast
 10) Wavelength Assignment Method (Random -1, First Fit -2): Random wavelength assignment picks a wavelength out of available ones and First-Fit selects the wavelength with lowest index first
 11) Latency Thershold in milli seconds: All the lightpath connections that inccur more than this latency will be blocked (dropped).

-------------------
Viewing the Results:
-------------------
Results can be viewed in a folder created during the simulation ../output

---------------------------
Files used in the simulator
--------------------------
       + main.m
       |----- timing.m  
       |---- + arrive.m
             |---- RandSD.m
             |---- sorting.m
       |---- departure.m
       |---- configureOXC.m
       |---- deconfigureOXC.m
       |---- dijkstra.m
       |---- + crosstalk.m
             |---- nxt.m
             |---- mb2bin.m
             |---- num_bin.m
       |---- wave_assign.m
       |---- + phy_topology.m
             |---- hop_mat.m          
       |---- exprnd.m
       |---- constants.m
       |---- imp_cons.m
       |---- paramters.m

This review did not use the simulation.

NetFPGA Hardware Source Code Package

The NetFPGA Hardware Source Code Package was unpacked:

$ unzip GENI_ERM_NetFPGA.zip 
$ cd GENI_ERM_NetFPGA/NF2

A README.txt is included which documents the following:

The hardware portion of the ERM Box code primarily used to actuate a semiconductor optical amplifier (SOA). 
This code is written using the existing netFPGA code structure. 
Please visit the NetFPGA wiki (http://netfpga.org/foswiki/bin/view/NetFPGA/OneGig/Guide#Obtaining_Gateware_Software_Pack) for more information on how to use it. 

+------------------------------------------------------------------------
| $Id$
| Description: Quick intro to NetFPGA
+------------------------------------------------------------------------

CONTENTS:
1.0 Tree structure
2.0 Getting started with design
        2.1 Using modules
        2.2 Adding your own code
        2.3 Overriding library code
        2.4 Coregen
3.0 Environment setup
4.0 Simulation
5.0 Implementation
6.0 Running the hardware
        6.1 Kernel Driver
        6.2 Download
7.0 Contacts

+-----------------------------------------------------------------------
| 1.0 Tree structure
+-----------------------------------------------------------------------
The tree is structured as follows:

NetFPGA2.1-x.y
|
+------ bin (contains scripts for running simulations 
|            and setting up the environment)
|
+------ lib (contains stable modules and common parts 
|       |    that are needed for simulation/synthesis/design)
|       |
|       +---- C (contains common software and code for reference designs)
|       |
|       +---- verilog (contains modules and files that can be reused for design)
|       |
|       +---- Makefiles (various makefiles for simulation and synthesis)
|       |
|       +---- Perl5 (contains common libraries to interact with 
|                    reference designs and aid in simulation)
|
+------ projects (contains user projects including the reference designs)
        |
        +---- geni_umf_v3_3pin
        |       |
        |       +---- src (contains all the verilog code to be used for 
        |       |          synthesis and simulation)
        |       |
        |       +---- synth (contains user .xco files to generate cores 
        |       |            and Makefile to implement the design)

        |       +---- lib (contains stable modules and common parts 
        |       |         that are needed for simulation/synthesis/design)
        |       |
        |       +---- regress(contain test scripts for running regression tests 
        |       |     on the hardware modules           
        |       |
        |       +---- include (contains files that define macros and other 
        |                files to be included for simulation and/or synthesis)
        |
        +---- other netfpga projects (reference 4-port IPv4 router, titled "reference_nic")
        |
         +---- CPCI2.1 (code for the Spartan device) 



The tree was design to enable modularity and common code sharing between the
library and the user projects.

The scripts used for synthesis and simulation should be flexible enough to
allow the user to add her own code without changing or understanding how the
scripts work. But this is outside the scope of this README.

+-----------------------------------------------------------------------
| 2.0 Getting started with Design
+-----------------------------------------------------------------------
The best way to learn how to use the tree is by example. If you look at
the geni_umf_v3_3pin project, you will notice several things:

1- The src directory contains two files: crytpo.v and user_data_path.v. These are the
   two verilog files that are created for the ERM Box NetFPGA code. 
2- The regress directory contains a number of regression tests to test this hardware
   module. 
3- There is one file under include: lib_modules.txt. This file specifies the
   library modules to use.

The best way to start a design is by copying either the reference_switch or the
reference_router directories and adding/modifying files in the new directory.

* 2.1 USING LIBRARY MODULES
The lib_modules.txt file specifies a list of modules to use from the library.
The modules are specified relative to the NetFPGA2.1-x.y/lib/verilog directory.
You can choose to use different modules simply by changing the module path in 
the lib_modules.txt file.

* 2.2 ADDING YOUR OWN CODE
To add your own code, write the verilog files and put them in the src directory.
You can also choose to partition them into separate directories under src. Note
that only one level of hierarchy is usable.

You can choose to use some, all, or even none of the original library modules.
You can copy the library code and modify it in your project directory. Take out
the library modules you are not using from the lib_modules.txt file.

* 2.3 OVERRIDING LIBRARY CODE
You might decide that you only need to change one file of a library module. You
don't need to copy all the sources and remove the library module from 
lib_modules.txt. Simply copy the file you wish to modify to your project's src
directory and modify it there.

* 2.4 COREGEN
If you need to use IP cores generated with Xilinx's Coregen, copy the .xco file
that was generated to your project's synth directory. You don't need any of the
other files. The scripts will take care of it.

+-----------------------------------------------------------------------
| 3.0 Environment setup
+-----------------------------------------------------------------------
The following environment variables need to be set:

NF2_ROOT - set to the root directory of the tree (NetFPGA2.1-x.y)
NF2_DESIGN_DIR - set to the project's directory (e.g. $NF2_ROOT/projects/reference_nic)
NF2_WORK_DIR - set to the working directory (somewhere with lots of space)

If you are running BASH you will then need to source 
${NF2_ROOT}/lib/bin/nf2_profile. Otherwise, if you are running CSH then 
you will need to source ${NF2_ROOT}/lib/bin/nf2_cshrc.

NOTE: Please make sure that the settings in these two files correspond
to your setup. THE DEFAULTS WILL *NOT* WORK!

+-----------------------------------------------------------------------
| 4.0 Simulation
+-----------------------------------------------------------------------
To simulate your design, there are several libraries to help. Take a look
at reference_router/verif/test_router_full to see how to use the perl
library functions. To create your own testbench, copy one of the test_*
directories and make sure its name has 3 parts test_major_minor. You
can then modify the make_pkts file to your liking.

The Perl libraries used live in lib/Perl5. You can add your own libraries
your project's verif/src dir.

To run the simulation, use the following command:
nf21_run_test.pl --major x --minor y

To run it with a gui, add the --gui switch. Type nf21_run_test.pl --help
for full details.

NOTE: coregen needs X. Make sure that you are running from a graphical 
console if IP cores are being built (for example the first time you are
simulating or implementing a design.)

+-----------------------------------------------------------------------
| 5.0 Implementation
+-----------------------------------------------------------------------
To implement your design, cd to the synth directory and type make. If all
goes well, you should end up with nf2_top_par.bit file that you can use 
to download to the FPGA.

If problems occur, make sure that you have all the .xco files for the user 
generated IP cores in the synth directory. Make sure to look at nf2_top_par.twr
to make sure that your design has passed timing checks. Also make sure to
heed the note in section 4.0 above.

+-----------------------------------------------------------------------
| 6.0 Running the hardware
+-----------------------------------------------------------------------
To run the hardware, there are two steps:
1- load the kernel module
2- download the .bin file

* 6.1 KERNEL DRIVER
1- cd to the lib/C/kernel directory, and type make.
2- as root, type insmod nf2.ko

If all goes well, you should see nf2c0, nf2c1, nf2c2, and nf2c3 when you do
ifconfig -a. If not, check that the card is plugged in properly and see if
it is identified by the lspci command.

* 6.2 DOWNLOAD
1- cd to lib/C/download and type make
2- as root, type nf2_download /path/to/nf2_top_par.bin

That's it! Your hardware is loaded on the device and should be working.
Browse through the tools under lib/C/switch, lib/C/router, and lib/C/tools
for tools to use to interact with real hardware.

+-----------------------------------------------------------------------
| 7.0 Contacts 
+-----------------------------------------------------------------------
- Jad Naous <first initial last name at stanford period edu> 
        For reference design questions, library modules, synthesis and 
        simulation makefile questions.
- Glen Gibb <first initial r last initial at stanford period edu>
        For board problems and simulation Perl libraries.

The review of the README conclude the second evaluation; Software evaluation was not possible.

Initial Evaluation

For the first evaluation, both packages were unpacked to review enclosed documentations as well as checking for any potential packaging issues. To unpack the simulation package executed the following:

 $ unzip GENI\ 10\ Simulations\ 2.zip 
 $ cd GENI\ 10\ Simulations\ 2/

The simulation package includes a README.txt that states the following:

GENI and Columbia University proprietary
Authors: Lightwave Research Laboratory
Last Modified: March 2011
All rights reserved
Discrete Event Simulations of Optical Mesh Network 
**********************************************************************************
Release: Version 1
Date:  March 2011.
Contact Email: bbathula@ee.columbia.edu; bgsquare@gmail.com
 
----------------------------------------------------------------------------------
Disclaimer: This software does not come with guarantees !
----------------------------------------------------------------------------------

----------------------------------------
Functionalities present in this release:
----------------------------------------
* Discrete event simulations of optical mesh networks.
* Events are the arrival and departure of the lightpath demands according to the Poission 
distribution and exponential service times.
* This simulator can perform, unicast, multicast, anycast and manycast communication paradigms. In the case of multicast, the light-trees are configured in the network, where the optical switches (ROADMS) perform the light splitting.
* The routing used in the simulator is Shortest-path (OSPF) and the wavelength assigments can be random or first-fit.
* Impairment-aware RWA algorithms are implemented via a Quality-of-Transmission (QoT) estimator.
* Rudimentary energy models are implemented for the optical physical layer.
* Control signaling latencies are modeled.
* Simulator can be scalable to wavelengths and the network topologies.
* Large scale mesh networks are considered.

----------------------
Running the simulator:
----------------------
* The main file is "main.m". 
* The input parameters file used to run the "main.m"  is "InputParam.txt"
* The file "InputParam.txt" consists of the description of the parameters and their values.

Unpacked the NetFPGA package:

 $ unzip geni_umf_v3_3pin.zip 
 $ cd geni_umf_v3_3pin/geni_umf_v3_3pin/

The NetFPGA package includes a README_ERM_Updated.txt file which states:

The hardware portion of the ERM Box code primarily used to actuate a semiconductor optical
 amplifier (SOA). 
This code is written using the existing NetFPGA code structure. 
Please visit the NetFPGA wiki (http://netfpga.org/foswiki/bin/view/NetFPGA/OneGig/Guide#Ob
taining_Gateware_Software_Pack) for more information on how to use it. 

+------------------------------------------------------------------------
| $Id$
| 
| Description: Quick intro to NetFPGA
+------------------------------------------------------------------------

CONTENTS:
1.0 Tree structure
2.0 Getting started with design
        2.1 Using modules
        2.2 Adding your own code
        2.3 Overriding library code
        2.4 Coregen
3.0 Environment setup
4.0 Simulation
5.0 Implementation
6.0 Running the hardware
        6.1 Kernel Driver
        6.2 Download
7.0 Contacts

+-----------------------------------------------------------------------
| 1.0 Tree structure
+-----------------------------------------------------------------------

The tree is structured as follows:


NetFPGA2.1-x.y
|
+------ bin (contains scripts for running simulations 
|            and setting up the environment)
|
+------ lib (contains stable modules and common parts 
|       |    that are needed for simulation/synthesis/design)
|       |
|       +---- C (contains common software and code for reference designs)
|       |
|       +---- verilog (contains modules and files that can be reused for design)
|       |
|       +---- Makefiles (various makefiles for simulation and synthesis)
|       |
|       +---- Perl5 (contains common libraries to interact with 
|                    reference designs and aid in simulation)
|
+------ projects (contains user projects including the reference designs)
        |
        +---- geni_umf_v3_3pin
        |       |
        |       +---- src (contains all the verilog code to be used for 
        |       |          synthesis and simulation)
        |       |
        |       +---- synth (contains user .xco files to generate cores 
        |       |            and Makefile to implement the design)
        |       |
        |       +---- sw (contains all software parts for the project)
        |       |
        |       +---- include (contains files that define macros and other 
        |                files to be included for simulation and/or synthesis)
        |
        +---- other netfpga projects (reference 4-port IPv4 router)
        |
        +---- CPCI2.1 (code for the Spartan device) 

The tree was design to enable modularity and common code sharing between the
library and the user projects.

The scripts used for synthesis and simulation should be flexible enough to
allow the user to add her own code without changing or understanding how the
scripts work. But this is outside the scope of this README.

+-----------------------------------------------------------------------
| 2.0 Getting started with Design
+-----------------------------------------------------------------------
The best way to learn how to use the tree is by example. If you look at
the reference_nic project, you will notice several things:
1- The src directory is empty: This is because the project only uses
   library modules.
2- The sw directory is empty: This is because the software for the
   switch is also in the library
3- There is one file under include: lib_modules.txt. This file specifies the
   library modules to use.

The best way to start a design is by copying either the reference_switch or the
reference_router directories and adding/modifying files in the new directory.

* 2.1 USING LIBRARY MODULES

The lib_modules.txt file specifies a list of modules to use from the library.
The modules are specified relative to the NetFPGA2.1-x.y/lib/verilog directory.
You can choose to use different modules simply by changing the module path in 
the lib_modules.txt file.

* 2.2 ADDING YOUR OWN CODE

To add your own code, write the verilog files and put them in the src directory.
You can also choose to partition them into separate directories under src. Note
that only one level of hierarchy is usable.

You can choose to use some, all, or even none of the original library modules.
You can copy the library code and modify it in your project directory. Take out
the library modules you are not using from the lib_modules.txt file.

* 2.3 OVERRIDING LIBRARY CODE

You might decide that you only need to change one file of a library module. You
don't need to copy all the sources and remove the library module from 
lib_modules.txt. Simply copy the file you wish to modify to your project's src
directory and modify it there.

* 2.4 COREGEN

If you need to use IP cores generated with Xilinx's Coregen, copy the .xco file
that was generated to your project's synth directory. You don't need any of the
other files. The scripts will take care of it.

+-----------------------------------------------------------------------
| 3.0 Environment setup
+-----------------------------------------------------------------------
The following environment variables need to be set:

NF2_ROOT - set to the root directory of the tree (NetFPGA2.1-x.y)
NF2_DESIGN_DIR - set to the project's directory 
                 (e.g. $NF2_ROOT/projects/reference_nic)
NF2_WORK_DIR - set to the working directory (somewhere with lots of space)

If you are running BASH you will then need to source 
${NF2_ROOT}/lib/bin/nf2_profile. Otherwise, if you are running CSH then 
you will need to source ${NF2_ROOT}/lib/bin/nf2_cshrc.

NOTE: Please make sure that the settings in these two files correspond
to your setup. THE DEFAULTS WILL *NOT* WORK!

+-----------------------------------------------------------------------
| 4.0 Simulation
+-----------------------------------------------------------------------

To simulate your design, there are several libraries to help. Take a look
at reference_router/verif/test_router_full to see how to use the perl
library functions. To create your own testbench, copy one of the test_*
directories and make sure its name has 3 parts test_major_minor. You
can then modify the make_pkts file to your liking.

The Perl libraries used live in lib/Perl5. You can add your own libraries
your project's verif/src dir.

To run the simulation, use the following command:
nf21_run_test.pl --major x --minor y

To run it with a gui, add the --gui switch. Type nf21_run_test.pl --help
for full details.

NOTE: coregen needs X. Make sure that you are running from a graphical 
console if IP cores are being built (for example the first time you are
simulating or implementing a design.)

+-----------------------------------------------------------------------
| 5.0 Implementation
+-----------------------------------------------------------------------

To implement your design, cd to the synth directory and type make. If all
goes well, you should end up with nf2_top_par.bit file that you can use 
to download to the FPGA.

If problems occur, make sure that you have all the .xco files for the user 
generated IP cores in the synth directory. Make sure to look at nf2_top_par.twr
to make sure that your design has passed timing checks. Also make sure to
heed the note in section 4.0 above.

+-----------------------------------------------------------------------
| 6.0 Running the hardware
+-----------------------------------------------------------------------

To run the hardware, there are two steps:
1- load the kernel module
2- download the .bin file

* 6.1 KERNEL DRIVER
1- cd to the lib/C/kernel directory, and type make.
2- as root, type insmod nf2.ko

If all goes well, you should see nf2c0, nf2c1, nf2c2, and nf2c3 when you do
ifconfig -a. If not, check that the card is plugged in properly and see if
it is identified by the lspci command.

* 6.2 DOWNLOAD
1- cd to lib/C/download and type make
2- as root, type nf2_download /path/to/nf2_top_par.bin

That's it! Your hardware is loaded on the device and should be working.
Browse through the tools under lib/C/switch, lib/C/router, and lib/C/tools
for tools to use to interact with real hardware.

+-----------------------------------------------------------------------
| 7.0 Contacts 
+-----------------------------------------------------------------------

- Jad Naous <first initial last name at stanford period edu> 
        For reference design questions, library modules, synthesis and 
        simulation makefile questions.

- Glen Gibb <first initial r last initial at stanford period edu>
        For board problems and simulation Perl libraries.

The review of the package content found some issues which are captured in the attached email exchanges.



Email us with any questions and feedback on this page!

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