Changes between Version 7 and Version 8 of GIR3.2_ERM


Ignore:
Timestamp:
10/24/11 11:04:06 (8 years ago)
Author:
lnevers@bbn.com
Comment:

--

Legend:

Unmodified
Added
Removed
Modified
  • GIR3.2_ERM

    v7 v8  
    1010 * [attachment: ERM-Feedback-20111024.txt]
    1111
     12Currently working on resolving issues.
     13
     14
    1215= Embedded Real-Time Measurements How-to =
    1316
    14 Unapack Simulation file:
    15 {{{
    16  $ unzip GENI\ 10\ Simulations.zip
    17 }}}
    18 
    19 Unpack Netfpga file:
    20 {{{
    21 sudo apt-get install unrar
    22 $ unrar e geni_umf_v3_3pin.rar
    23 
    24 UNRAR 3.90 beta 2 freeware      Copyright (c) 1993-2009 Alexander Roshal
    25 
    26 
    27 Extracting from geni_umf_v3_3pin.rar
    28 
    29 Extracting  make_pkts.pl                                              OK
    30 Extracting  config.txt                                                OK
    31 
    32 make_pkts.pl already exists. Overwrite it ?
    33 }}}
     17Unpack Simulation package:
     18{{{
     19 $ unzip GENI\ 10\ Simulations\ 2.zip
     20 $ cd GENI\ 10\ Simulations\ 2/
     21}}}
     22The package includes a README.txt that states the following:
     23{{{
     24GENI and Columbia University proprietary
     25Authors: Lightwave Research Laboratory
     26Last Modified: March 2011
     27All rights reserved
     28Discrete Event Simulations of Optical Mesh Network
     29**********************************************************************************
     30Release: Version 1
     31Date:  March 2011.
     32Contact Email: bbathula@ee.columbia.edu; bgsquare@gmail.com
     33 
     34----------------------------------------------------------------------------------
     35Disclaimer: This software does not come with guarantees !
     36----------------------------------------------------------------------------------
     37
     38----------------------------------------
     39Functionalities present in this release:
     40----------------------------------------
     41* Discrete event simulations of optical mesh networks.
     42* Events are the arrival and departure of the lightpath demands according to the Poission
     43distribution and exponential service times.
     44* This simulator can perform, unicast, multicast, anycast and manycast communication parad
     45igms. In the case of multicast, the light-trees are configured in the network, where the o
     46ptical switches (ROADMS) perform the light splitting.
     47* The routing used in the simulator is Shortest-path (OSPF) and the wavelength assigments
     48can be random or first-fit.
     49* Impairment-aware RWA algorithms are implemented via a Quality-of-Transmission (QoT) esti
     50mator.
     51* Rudimentary energy models are implemented for the optical physical layer.
     52* Control signaling latencies are modeled.
     53* Simulator can be scalable to wavelengths and the network topologies.
     54* Large scale mesh networks are considered.
     55
     56----------------------
     57Running the simulator:
     58----------------------
     59* The main file is "main.m".
     60* The input parameters file used to run the "main.m"  is "InputParam.txt"
     61* The file "InputParam.txt" consists of the description of the parameters and their values.
     62}}}
     63
     64Unpack Netfpga package:
     65{{{
     66 $ unzip geni_umf_v3_3pin.zip
     67 $ cd geni_umf_v3_3pin/geni_umf_v3_3pin/
     68}}}
     69The Netfpga package includes a  README_ERM_Updated.txt file which states:
     70{{{
     71The hardware portion of the ERM Box code primarily used to actuate a semiconductor optical
     72 amplifier (SOA).
     73This code is written using the existing netFPGA code structure.
     74Please visit the NetFPGA wiki (http://netfpga.org/foswiki/bin/view/NetFPGA/OneGig/Guide#Ob
     75taining_Gateware_Software_Pack) for more information on how to use it.
     76
     77+------------------------------------------------------------------------
     78| $Id$
     79|
     80| Description: Quick intro to NetFPGA
     81+------------------------------------------------------------------------
     82
     83CONTENTS:
     841.0 Tree structure
     852.0 Getting started with design
     86        2.1 Using modules
     87        2.2 Adding your own code
     88        2.3 Overriding library code
     89        2.4 Coregen
     903.0 Environment setup
     914.0 Simulation
     925.0 Implementation
     936.0 Running the hardware
     94        6.1 Kernel Driver
     95        6.2 Download
     967.0 Contacts
     97
     98+-----------------------------------------------------------------------
     99| 1.0 Tree structure
     100+-----------------------------------------------------------------------
     101
     102The tree is structured as follows:
     103
     104
     105NetFPGA2.1-x.y
     106|
     107+------ bin (contains scripts for running simulations
     108|            and setting up the environment)
     109|
     110+------ lib (contains stable modules and common parts
     111|       |    that are needed for simulation/synthesis/design)
     112|       |
     113|       +---- C (contains common software and code for reference designs)
     114|       |
     115|       +---- verilog (contains modules and files that can be reused for design)
     116|       |
     117|       +---- Makefiles (various makefiles for simulation and synthesis)
     118|       |
     119|       +---- Perl5 (contains common libraries to interact with
     120|                    reference designs and aid in simulation)
     121|
     122+------ projects (contains user projects including the reference designs)
     123        |
     124        +---- geni_umf_v3_3pin
     125        |       |
     126        |       +---- src (contains all the verilog code to be used for
     127        |       |          synthesis and simulation)
     128        |       |
     129        |       +---- synth (contains user .xco files to generate cores
     130        |       |            and Makefile to implement the design)
     131        |       |
     132        |       +---- sw (contains all software parts for the project)
     133        |       |
     134        |       +---- include (contains files that define macros and other
     135        |                files to be included for simulation and/or synthesis)
     136        |
     137        +---- other netfpga projects (reference 4-port IPv4 router)
     138        |
     139        +---- CPCI2.1 (code for the Spartan device)
     140
     141he tree was design to enable modularity and common code sharing between the
     142library and the user projects.
     143
     144The scripts used for synthesis and simulation should be flexible enough to
     145allow the user to add her own code without changing or understanding how the
     146scripts work. But this is outside the scope of this README.
     147
     148+-----------------------------------------------------------------------
     149| 2.0 Getting started with Design
     150+-----------------------------------------------------------------------
     151The best way to learn how to use the tree is by example. If you look at
     152the reference_nic project, you will notice several things:
     1531- The src directory is empty: This is because the project only uses
     154   library modules.
     1552- The sw directory is empty: This is because the software for the
     156   switch is also in the library
     1573- There is one file under include: lib_modules.txt. This file specifies the
     158   library modules to use.
     159
     160The best way to start a design is by copying either the reference_switch or the
     161reference_router directories and adding/modifying files in the new directory.
     162
     163* 2.1 USING LIBRARY MODULES
     164
     165The lib_modules.txt file specifies a list of modules to use from the library.
     166The modules are specified relative to the NetFPGA2.1-x.y/lib/verilog directory.
     167You can choose to use different modules simply by changing the module path in
     168the lib_modules.txt file.
     169
     170* 2.2 ADDING YOUR OWN CODE
     171
     172To add your own code, write the verilog files and put them in the src directory.
     173You can also choose to partition them into separate directories under src. Note
     174that only one level of hierarchy is usable.
     175
     176You can choose to use some, all, or even none of the original library modules.
     177You can copy the library code and modify it in your project directory. Take out
     178the library modules you are not using from the lib_modules.txt file.
     179
     180* 2.3 OVERRIDING LIBRARY CODE
     181
     182You might decide that you only need to change one file of a library module. You
     183don't need to copy all the sources and remove the library module from
     184lib_modules.txt. Simply copy the file you wish to modify to your project's src
     185directory and modify it there.
     186
     187* 2.4 COREGEN
     188
     189If you need to use IP cores generated with Xilinx's Coregen, copy the .xco file
     190that was generated to your project's synth directory. You don't need any of the
     191other files. The scripts will take care of it.
     192
     193+-----------------------------------------------------------------------
     194| 3.0 Environment setup
     195+-----------------------------------------------------------------------
     196The following environment variables need to be set:
     197
     198NF2_ROOT - set to the root directory of the tree (NetFPGA2.1-x.y)
     199NF2_DESIGN_DIR - set to the project's directory
     200                 (e.g. $NF2_ROOT/projects/reference_nic)
     201NF2_WORK_DIR - set to the working directory (somewhere with lots of space)
     202
     203If you are running BASH you will then need to source
     204${NF2_ROOT}/lib/bin/nf2_profile. Otherwise, if you are running CSH then
     205you will need to source ${NF2_ROOT}/lib/bin/nf2_cshrc.
     206
     207NOTE: Please make sure that the settings in these two files correspond
     208to your setup. THE DEFAULTS WILL *NOT* WORK!
     209
     210+-----------------------------------------------------------------------
     211| 4.0 Simulation
     212+-----------------------------------------------------------------------
     213
     214To simulate your design, there are several libraries to help. Take a look
     215at reference_router/verif/test_router_full to see how to use the perl
     216library functions. To create your own testbench, copy one of the test_*
     217directories and make sure its name has 3 parts test_major_minor. You
     218can then modify the make_pkts file to your liking.
     219
     220The Perl libraries used live in lib/Perl5. You can add your own libraries
     221your project's verif/src dir.
     222
     223To run the simulation, use the following command:
     224nf21_run_test.pl --major x --minor y
     225
     226To run it with a gui, add the --gui switch. Type nf21_run_test.pl --help
     227for full details.
     228
     229NOTE: coregen needs X. Make sure that you are running from a graphical
     230console if IP cores are being built (for example the first time you are
     231simulating or implementing a design.)
     232
     233+-----------------------------------------------------------------------
     234| 5.0 Implementation
     235+-----------------------------------------------------------------------
     236
     237To implement your design, cd to the synth directory and type make. If all
     238goes well, you should end up with nf2_top_par.bit file that you can use
     239to download to the FPGA.
     240
     241If problems occur, make sure that you have all the .xco files for the user
     242generated IP cores in the synth directory. Make sure to look at nf2_top_par.twr
     243to make sure that your design has passed timing checks. Also make sure to
     244heed the note in section 4.0 above.
     245
     246+-----------------------------------------------------------------------
     247| 6.0 Running the hardware
     248+-----------------------------------------------------------------------
     249
     250To run the hardware, there are two steps:
     2511- load the kernel module
     2522- download the .bin file
     253
     254* 6.1 KERNEL DRIVER
     2551- cd to the lib/C/kernel directory, and type make.
     2562- as root, type insmod nf2.ko
     257
     258If all goes well, you should see nf2c0, nf2c1, nf2c2, and nf2c3 when you do
     259ifconfig -a. If not, check that the card is plugged in properly and see if
     260it is identified by the lspci command.
     261
     262* 6.2 DOWNLOAD
     2631- cd to lib/C/download and type make
     2642- as root, type nf2_download /path/to/nf2_top_par.bin
     265
     266That's it! Your hardware is loaded on the device and should be working.
     267Browse through the tools under lib/C/switch, lib/C/router, and lib/C/tools
     268for tools to use to interact with real hardware.
     269
     270+-----------------------------------------------------------------------
     271| 7.0 Contacts
     272+-----------------------------------------------------------------------
     273
     274- Jad Naous <first initial last name at stanford period edu>
     275        For reference design questions, library modules, synthesis and
     276        simulation makefile questions.
     277
     278- Glen Gibb <first initial r last initial at stanford period edu>
     279        For board problems and simulation Perl libraries.
     280}}}