Changes between Version 19 and Version 20 of GIR3.2_ERM
- Timestamp:
- 11/02/11 13:33:13 (12 years ago)
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GIR3.2_ERM
v19 v20 18 18 * [attachment: ERM-Feedback-20111024.txt] 19 19 * [attachment: ERM-Feedback-20111024a.txt] 20 21 20 A second evaluation was completed after new packages were made available on November 1, 2011. 22 21 23 24 22 = Embedded Real-Time Measurements How-to = 25 23 26 Second Evaluation'''24 '''Second Evaluation''' 27 25 Two Packages were made available for the second ERM evaluation: 28 26 * [http://groups.geni.net/geni/attachment/wiki/Embedded%20Real-Time%20Measurements/ERM-Simulator.v.1.zip?format=raw Simulation Source Code] … … 31 29 ==Simulation Source Code Package == 32 30 33 Unpack the Simulation Source Code Package:31 Unpacked the Simulation Source Code Package: 34 32 {{{ 35 33 $ unzip ERM-Simulator.v.1.zip … … 123 121 * Events are the arrival and departure of the lightpath demands according to the Poission distribution and exponential service times. 124 122 * This simulator can perform, unicast, anycast communication paradigms. In the case of multicast, the light-trees are configured in the network, where the optical switches (ROADMS) perform the light splitting. 125 * The routing used in the simulator is Shortest-path (OSPF) and the wavelength assig ments can be random or first-fit.123 * The routing used in the simulator is Shortest-path (OSPF) and the wavelength assignments can be random or first-fit. 126 124 * Impairment-aware RWA algorithms are implemented via a Quality-of-Transmission (QoT) estimator. 127 125 * Rudimentary energy models are implemented for the optical physical layer. … … 151 149 ------------------- 152 150 Viewing the Results: 153 ------------------ 151 ------------------- 154 152 Results can be viewed in a folder created during the simulation ../output 155 153 … … 187 185 $ cd GENI_ERM_NetFPGA/NF2 188 186 }}} 189 190 187 A README.txt is included which documents the following: 191 188 {{{ 192 189 The hardware portion of the ERM Box code primarily used to actuate a semiconductor optical amplifier (SOA). 193 190 This code is written using the existing netFPGA code structure. 194 Please visit the NetFPGA wiki (http://netfpga.org/foswiki/bin/view/NetFPGA/OneGig/Guide#Obtaining_Gateware_Software_Pack) for more informat 195 ion on how to use it. 191 Please visit the NetFPGA wiki (http://netfpga.org/foswiki/bin/view/NetFPGA/OneGig/Guide#Obtaining_Gateware_Software_Pack) for more information on how to use it. 196 192 197 193 +------------------------------------------------------------------------ 198 194 | $Id$ 199 |200 195 | Description: Quick intro to NetFPGA 201 196 +------------------------------------------------------------------------ … … 219 214 | 1.0 Tree structure 220 215 +----------------------------------------------------------------------- 221 222 216 The tree is structured as follows: 223 224 217 225 218 NetFPGA2.1-x.y … … 277 270 The best way to learn how to use the tree is by example. If you look at 278 271 the geni_umf_v3_3pin project, you will notice several things: 272 279 273 1- The src directory contains two files: crytpo.v and user_data_path.v. These are the 280 274 two verilog files that are created for the ERM Box NetFPGA code. … … 288 282 289 283 * 2.1 USING LIBRARY MODULES 290 291 284 The lib_modules.txt file specifies a list of modules to use from the library. 292 285 The modules are specified relative to the NetFPGA2.1-x.y/lib/verilog directory. … … 295 288 296 289 * 2.2 ADDING YOUR OWN CODE 297 298 290 To add your own code, write the verilog files and put them in the src directory. 299 291 You can also choose to partition them into separate directories under src. Note … … 305 297 306 298 * 2.3 OVERRIDING LIBRARY CODE 307 308 299 You might decide that you only need to change one file of a library module. You 309 300 don't need to copy all the sources and remove the library module from … … 312 303 313 304 * 2.4 COREGEN 314 315 305 If you need to use IP cores generated with Xilinx's Coregen, copy the .xco file 316 306 that was generated to your project's synth directory. You don't need any of the … … 323 313 324 314 NF2_ROOT - set to the root directory of the tree (NetFPGA2.1-x.y) 325 NF2_DESIGN_DIR - set to the project's directory 326 (e.g. $NF2_ROOT/projects/reference_nic) 315 NF2_DESIGN_DIR - set to the project's directory (e.g. $NF2_ROOT/projects/reference_nic) 327 316 NF2_WORK_DIR - set to the working directory (somewhere with lots of space) 328 317 … … 334 323 to your setup. THE DEFAULTS WILL *NOT* WORK! 335 324 336 337 325 +----------------------------------------------------------------------- 338 326 | 4.0 Simulation 339 327 +----------------------------------------------------------------------- 340 341 328 To simulate your design, there are several libraries to help. Take a look 342 329 at reference_router/verif/test_router_full to see how to use the perl … … 361 348 | 5.0 Implementation 362 349 +----------------------------------------------------------------------- 363 364 350 To implement your design, cd to the synth directory and type make. If all 365 351 goes well, you should end up with nf2_top_par.bit file that you can use … … 374 360 | 6.0 Running the hardware 375 361 +----------------------------------------------------------------------- 376 377 362 To run the hardware, there are two steps: 378 363 1- load the kernel module … … 398 383 | 7.0 Contacts 399 384 +----------------------------------------------------------------------- 400 401 385 - Jad Naous <first initial last name at stanford period edu> 402 386 For reference design questions, library modules, synthesis and 403 387 simulation makefile questions. 404 405 388 - Glen Gibb <first initial r last initial at stanford period edu> 406 389 For board problems and simulation Perl libraries. 407 390 }}} 391 392 The review of the README conclude the second evaluation; Software evaluation was not possible. 408 393 409 394