197 | | |
198 | | '''First Evaluation''' |
199 | | |
200 | | Both packages were unpacked to review enclosed documentations as well as checking for any potential packaging issues. To unpack the simulation package executed the following: |
201 | | {{{ |
202 | | $ unzip GENI\ 10\ Simulations\ 2.zip |
203 | | $ cd GENI\ 10\ Simulations\ 2/ |
204 | | }}} |
205 | | The simulation package includes a README.txt that states the following: |
206 | | {{{ |
207 | | GENI and Columbia University proprietary |
208 | | Authors: Lightwave Research Laboratory |
209 | | Last Modified: March 2011 |
210 | | All rights reserved |
211 | | Discrete Event Simulations of Optical Mesh Network |
212 | | ********************************************************************************** |
213 | | Release: Version 1 |
214 | | Date: March 2011. |
215 | | Contact Email: bbathula@ee.columbia.edu; bgsquare@gmail.com |
216 | | |
217 | | ---------------------------------------------------------------------------------- |
218 | | Disclaimer: This software does not come with guarantees ! |
219 | | ---------------------------------------------------------------------------------- |
220 | | |
221 | | ---------------------------------------- |
222 | | Functionalities present in this release: |
223 | | ---------------------------------------- |
224 | | * Discrete event simulations of optical mesh networks. |
225 | | * Events are the arrival and departure of the lightpath demands according to the Poission |
226 | | distribution and exponential service times. |
227 | | * This simulator can perform, unicast, multicast, anycast and manycast communication paradigms. In the case of multicast, the light-trees are configured in the network, where the optical switches (ROADMS) perform the light splitting. |
228 | | * The routing used in the simulator is Shortest-path (OSPF) and the wavelength assigments can be random or first-fit. |
229 | | * Impairment-aware RWA algorithms are implemented via a Quality-of-Transmission (QoT) estimator. |
230 | | * Rudimentary energy models are implemented for the optical physical layer. |
231 | | * Control signaling latencies are modeled. |
232 | | * Simulator can be scalable to wavelengths and the network topologies. |
233 | | * Large scale mesh networks are considered. |
234 | | |
235 | | ---------------------- |
236 | | Running the simulator: |
237 | | ---------------------- |
238 | | * The main file is "main.m". |
239 | | * The input parameters file used to run the "main.m" is "InputParam.txt" |
240 | | * The file "InputParam.txt" consists of the description of the parameters and their values. |
241 | | }}} |
242 | | |
243 | | Unpacked the NetFPGA package: |
244 | | {{{ |
245 | | $ unzip geni_umf_v3_3pin.zip |
246 | | $ cd geni_umf_v3_3pin/geni_umf_v3_3pin/ |
247 | | }}} |
248 | | The NetFPGA package includes a README_ERM_Updated.txt file which states: |
249 | | {{{ |
250 | | The hardware portion of the ERM Box code primarily used to actuate a semiconductor optical |
251 | | amplifier (SOA). |
252 | | This code is written using the existing NetFPGA code structure. |
253 | | Please visit the NetFPGA wiki (http://netfpga.org/foswiki/bin/view/NetFPGA/OneGig/Guide#Ob |
254 | | taining_Gateware_Software_Pack) for more information on how to use it. |
| 184 | The NetFPGA Hardware Source Code Package was unpacked: |
| 185 | {{{ |
| 186 | $ unzip GENI_ERM_NetFPGA.zip |
| 187 | $ cd GENI_ERM_NetFPGA/NF2 |
| 188 | }}} |
| 189 | |
| 190 | A README.txt is included which documents the following: |
| 191 | {{{ |
| 192 | The hardware portion of the ERM Box code primarily used to actuate a semiconductor optical amplifier (SOA). |
| 193 | This code is written using the existing netFPGA code structure. |
| 194 | Please visit the NetFPGA wiki (http://netfpga.org/foswiki/bin/view/NetFPGA/OneGig/Guide#Obtaining_Gateware_Software_Pack) for more informat |
| 195 | ion on how to use it. |
| 251 | |
| 252 | | +---- lib (contains stable modules and common parts |
| 253 | | | that are needed for simulation/synthesis/design) |
| 254 | | | |
| 255 | | +---- regress(contain test scripts for running regression tests |
| 256 | | | on the hardware modules |
| 257 | | | |
| 258 | | +---- include (contains files that define macros and other |
| 259 | | files to be included for simulation and/or synthesis) |
| 260 | | |
| 261 | +---- other netfpga projects (reference 4-port IPv4 router, titled "reference_nic") |
| 262 | | |
| 263 | +---- CPCI2.1 (code for the Spartan device) |
| 264 | |
| 265 | |
| 266 | |
| 267 | The tree was design to enable modularity and common code sharing between the |
| 268 | library and the user projects. |
| 269 | |
| 270 | The scripts used for synthesis and simulation should be flexible enough to |
| 271 | allow the user to add her own code without changing or understanding how the |
| 272 | scripts work. But this is outside the scope of this README. |
| 273 | |
| 274 | +----------------------------------------------------------------------- |
| 275 | | 2.0 Getting started with Design |
| 276 | +----------------------------------------------------------------------- |
| 277 | The best way to learn how to use the tree is by example. If you look at |
| 278 | the geni_umf_v3_3pin project, you will notice several things: |
| 279 | 1- The src directory contains two files: crytpo.v and user_data_path.v. These are the |
| 280 | two verilog files that are created for the ERM Box NetFPGA code. |
| 281 | 2- The regress directory contains a number of regression tests to test this hardware |
| 282 | module. |
| 283 | 3- There is one file under include: lib_modules.txt. This file specifies the |
| 284 | library modules to use. |
| 285 | |
| 286 | The best way to start a design is by copying either the reference_switch or the |
| 287 | reference_router directories and adding/modifying files in the new directory. |
| 288 | |
| 289 | * 2.1 USING LIBRARY MODULES |
| 290 | |
| 291 | The lib_modules.txt file specifies a list of modules to use from the library. |
| 292 | The modules are specified relative to the NetFPGA2.1-x.y/lib/verilog directory. |
| 293 | You can choose to use different modules simply by changing the module path in |
| 294 | the lib_modules.txt file. |
| 295 | |
| 296 | * 2.2 ADDING YOUR OWN CODE |
| 297 | |
| 298 | To add your own code, write the verilog files and put them in the src directory. |
| 299 | You can also choose to partition them into separate directories under src. Note |
| 300 | that only one level of hierarchy is usable. |
| 301 | |
| 302 | You can choose to use some, all, or even none of the original library modules. |
| 303 | You can copy the library code and modify it in your project directory. Take out |
| 304 | the library modules you are not using from the lib_modules.txt file. |
| 305 | |
| 306 | * 2.3 OVERRIDING LIBRARY CODE |
| 307 | |
| 308 | You might decide that you only need to change one file of a library module. You |
| 309 | don't need to copy all the sources and remove the library module from |
| 310 | lib_modules.txt. Simply copy the file you wish to modify to your project's src |
| 311 | directory and modify it there. |
| 312 | |
| 313 | * 2.4 COREGEN |
| 314 | |
| 315 | If you need to use IP cores generated with Xilinx's Coregen, copy the .xco file |
| 316 | that was generated to your project's synth directory. You don't need any of the |
| 317 | other files. The scripts will take care of it. |
| 318 | |
| 319 | +----------------------------------------------------------------------- |
| 320 | | 3.0 Environment setup |
| 321 | +----------------------------------------------------------------------- |
| 322 | The following environment variables need to be set: |
| 323 | |
| 324 | NF2_ROOT - set to the root directory of the tree (NetFPGA2.1-x.y) |
| 325 | NF2_DESIGN_DIR - set to the project's directory |
| 326 | (e.g. $NF2_ROOT/projects/reference_nic) |
| 327 | NF2_WORK_DIR - set to the working directory (somewhere with lots of space) |
| 328 | |
| 329 | If you are running BASH you will then need to source |
| 330 | ${NF2_ROOT}/lib/bin/nf2_profile. Otherwise, if you are running CSH then |
| 331 | you will need to source ${NF2_ROOT}/lib/bin/nf2_cshrc. |
| 332 | |
| 333 | NOTE: Please make sure that the settings in these two files correspond |
| 334 | to your setup. THE DEFAULTS WILL *NOT* WORK! |
| 335 | |
| 336 | |
| 337 | +----------------------------------------------------------------------- |
| 338 | | 4.0 Simulation |
| 339 | +----------------------------------------------------------------------- |
| 340 | |
| 341 | To simulate your design, there are several libraries to help. Take a look |
| 342 | at reference_router/verif/test_router_full to see how to use the perl |
| 343 | library functions. To create your own testbench, copy one of the test_* |
| 344 | directories and make sure its name has 3 parts test_major_minor. You |
| 345 | can then modify the make_pkts file to your liking. |
| 346 | |
| 347 | The Perl libraries used live in lib/Perl5. You can add your own libraries |
| 348 | your project's verif/src dir. |
| 349 | |
| 350 | To run the simulation, use the following command: |
| 351 | nf21_run_test.pl --major x --minor y |
| 352 | |
| 353 | To run it with a gui, add the --gui switch. Type nf21_run_test.pl --help |
| 354 | for full details. |
| 355 | |
| 356 | NOTE: coregen needs X. Make sure that you are running from a graphical |
| 357 | console if IP cores are being built (for example the first time you are |
| 358 | simulating or implementing a design.) |
| 359 | |
| 360 | +----------------------------------------------------------------------- |
| 361 | | 5.0 Implementation |
| 362 | +----------------------------------------------------------------------- |
| 363 | |
| 364 | To implement your design, cd to the synth directory and type make. If all |
| 365 | goes well, you should end up with nf2_top_par.bit file that you can use |
| 366 | to download to the FPGA. |
| 367 | |
| 368 | If problems occur, make sure that you have all the .xco files for the user |
| 369 | generated IP cores in the synth directory. Make sure to look at nf2_top_par.twr |
| 370 | to make sure that your design has passed timing checks. Also make sure to |
| 371 | heed the note in section 4.0 above. |
| 372 | |
| 373 | +----------------------------------------------------------------------- |
| 374 | | 6.0 Running the hardware |
| 375 | +----------------------------------------------------------------------- |
| 376 | |
| 377 | To run the hardware, there are two steps: |
| 378 | 1- load the kernel module |
| 379 | 2- download the .bin file |
| 380 | |
| 381 | * 6.1 KERNEL DRIVER |
| 382 | 1- cd to the lib/C/kernel directory, and type make. |
| 383 | 2- as root, type insmod nf2.ko |
| 384 | |
| 385 | If all goes well, you should see nf2c0, nf2c1, nf2c2, and nf2c3 when you do |
| 386 | ifconfig -a. If not, check that the card is plugged in properly and see if |
| 387 | it is identified by the lspci command. |
| 388 | |
| 389 | * 6.2 DOWNLOAD |
| 390 | 1- cd to lib/C/download and type make |
| 391 | 2- as root, type nf2_download /path/to/nf2_top_par.bin |
| 392 | |
| 393 | That's it! Your hardware is loaded on the device and should be working. |
| 394 | Browse through the tools under lib/C/switch, lib/C/router, and lib/C/tools |
| 395 | for tools to use to interact with real hardware. |
| 396 | |
| 397 | +----------------------------------------------------------------------- |
| 398 | | 7.0 Contacts |
| 399 | +----------------------------------------------------------------------- |
| 400 | |
| 401 | - Jad Naous <first initial last name at stanford period edu> |
| 402 | For reference design questions, library modules, synthesis and |
| 403 | simulation makefile questions. |
| 404 | |
| 405 | - Glen Gibb <first initial r last initial at stanford period edu> |
| 406 | For board problems and simulation Perl libraries. |
| 407 | }}} |
| 408 | |
| 409 | |
| 410 | == Initial Evaluation == |
| 411 | |
| 412 | For the first evaluation, both packages were unpacked to review enclosed documentations as well as checking for any potential packaging issues. To unpack the simulation package executed the following: |
| 413 | {{{ |
| 414 | $ unzip GENI\ 10\ Simulations\ 2.zip |
| 415 | $ cd GENI\ 10\ Simulations\ 2/ |
| 416 | }}} |
| 417 | The simulation package includes a README.txt that states the following: |
| 418 | {{{ |
| 419 | GENI and Columbia University proprietary |
| 420 | Authors: Lightwave Research Laboratory |
| 421 | Last Modified: March 2011 |
| 422 | All rights reserved |
| 423 | Discrete Event Simulations of Optical Mesh Network |
| 424 | ********************************************************************************** |
| 425 | Release: Version 1 |
| 426 | Date: March 2011. |
| 427 | Contact Email: bbathula@ee.columbia.edu; bgsquare@gmail.com |
| 428 | |
| 429 | ---------------------------------------------------------------------------------- |
| 430 | Disclaimer: This software does not come with guarantees ! |
| 431 | ---------------------------------------------------------------------------------- |
| 432 | |
| 433 | ---------------------------------------- |
| 434 | Functionalities present in this release: |
| 435 | ---------------------------------------- |
| 436 | * Discrete event simulations of optical mesh networks. |
| 437 | * Events are the arrival and departure of the lightpath demands according to the Poission |
| 438 | distribution and exponential service times. |
| 439 | * This simulator can perform, unicast, multicast, anycast and manycast communication paradigms. In the case of multicast, the light-trees are configured in the network, where the optical switches (ROADMS) perform the light splitting. |
| 440 | * The routing used in the simulator is Shortest-path (OSPF) and the wavelength assigments can be random or first-fit. |
| 441 | * Impairment-aware RWA algorithms are implemented via a Quality-of-Transmission (QoT) estimator. |
| 442 | * Rudimentary energy models are implemented for the optical physical layer. |
| 443 | * Control signaling latencies are modeled. |
| 444 | * Simulator can be scalable to wavelengths and the network topologies. |
| 445 | * Large scale mesh networks are considered. |
| 446 | |
| 447 | ---------------------- |
| 448 | Running the simulator: |
| 449 | ---------------------- |
| 450 | * The main file is "main.m". |
| 451 | * The input parameters file used to run the "main.m" is "InputParam.txt" |
| 452 | * The file "InputParam.txt" consists of the description of the parameters and their values. |
| 453 | }}} |
| 454 | |
| 455 | Unpacked the NetFPGA package: |
| 456 | {{{ |
| 457 | $ unzip geni_umf_v3_3pin.zip |
| 458 | $ cd geni_umf_v3_3pin/geni_umf_v3_3pin/ |
| 459 | }}} |
| 460 | The NetFPGA package includes a README_ERM_Updated.txt file which states: |
| 461 | {{{ |
| 462 | The hardware portion of the ERM Box code primarily used to actuate a semiconductor optical |
| 463 | amplifier (SOA). |
| 464 | This code is written using the existing NetFPGA code structure. |
| 465 | Please visit the NetFPGA wiki (http://netfpga.org/foswiki/bin/view/NetFPGA/OneGig/Guide#Ob |
| 466 | taining_Gateware_Software_Pack) for more information on how to use it. |
| 467 | |
| 468 | +------------------------------------------------------------------------ |
| 469 | | $Id$ |
| 470 | | |
| 471 | | Description: Quick intro to NetFPGA |
| 472 | +------------------------------------------------------------------------ |
| 473 | |
| 474 | CONTENTS: |
| 475 | 1.0 Tree structure |
| 476 | 2.0 Getting started with design |
| 477 | 2.1 Using modules |
| 478 | 2.2 Adding your own code |
| 479 | 2.3 Overriding library code |
| 480 | 2.4 Coregen |
| 481 | 3.0 Environment setup |
| 482 | 4.0 Simulation |
| 483 | 5.0 Implementation |
| 484 | 6.0 Running the hardware |
| 485 | 6.1 Kernel Driver |
| 486 | 6.2 Download |
| 487 | 7.0 Contacts |
| 488 | |
| 489 | +----------------------------------------------------------------------- |
| 490 | | 1.0 Tree structure |
| 491 | +----------------------------------------------------------------------- |
| 492 | |
| 493 | The tree is structured as follows: |
| 494 | |
| 495 | |
| 496 | NetFPGA2.1-x.y |
| 497 | | |
| 498 | +------ bin (contains scripts for running simulations |
| 499 | | and setting up the environment) |
| 500 | | |
| 501 | +------ lib (contains stable modules and common parts |
| 502 | | | that are needed for simulation/synthesis/design) |
| 503 | | | |
| 504 | | +---- C (contains common software and code for reference designs) |
| 505 | | | |
| 506 | | +---- verilog (contains modules and files that can be reused for design) |
| 507 | | | |
| 508 | | +---- Makefiles (various makefiles for simulation and synthesis) |
| 509 | | | |
| 510 | | +---- Perl5 (contains common libraries to interact with |
| 511 | | reference designs and aid in simulation) |
| 512 | | |
| 513 | +------ projects (contains user projects including the reference designs) |
| 514 | | |
| 515 | +---- geni_umf_v3_3pin |
| 516 | | | |
| 517 | | +---- src (contains all the verilog code to be used for |
| 518 | | | synthesis and simulation) |
| 519 | | | |
| 520 | | +---- synth (contains user .xco files to generate cores |
| 521 | | | and Makefile to implement the design) |