1 | NetFPGA |
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2 | |
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3 | Nick McKeown |
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4 | |
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5 | We are building NetFPGA. Actually, we built the first version under an |
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6 | NSF-EIA program for use in teaching. It's being used quite a bit by |
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7 | us, and we are just about to launch support for other schools. NetFPGA |
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8 | 2.1 (available in Spring 2007) will consist of a design kit: |
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9 | |
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10 | * A PCI card that fits into a regular PC with 4 x 1GE ports and a |
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11 | honking great FPGA on it, |
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12 | |
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13 | * Design libraries in Verilog for common blocks (queues, schedulers, |
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14 | IP lookup, etc.). We will also supply standard designs, such as 4-port |
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15 | learning GE switch, 4-port GE router. |
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16 | |
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17 | * Courseware for people offering classes: Assignments and starter-code |
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18 | (we have a class called "Build an Internet Router" that uses this |
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19 | starter-code already. |
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20 | |
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21 | * Researchware for people doing research: Examples of packet |
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22 | generators, switches, monitoring, new algorithms and packet |
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23 | processing. |
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24 | |
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25 | The web site is: http://yuba.stanford.edu/netfpga |
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26 | |
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27 | How it helps GENI: |
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28 | |
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29 | While almost all graduating EE students are familiar with Verilog |
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30 | (just another parallel language :-) ), there is a small overlap |
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31 | between networking researchers and people who know Verilog. Our goal |
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32 | is to change that by making available a teaching tool for networking |
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33 | hardware that universities can use in ugrad and MS programs (as we are |
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34 | doing at Stanford), and for researchers who want to build their own |
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35 | modified switches/routers. |
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36 | |
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37 | By mid-2007 it should be possible to build the design kit above and |
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38 | for researchers to get experience programming their own switches and |
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39 | routers that process packets at line-rate. |
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